In many data processing applications, data is communicated between peripheral devices in a data processor and a memory. In general purpose systems which have a single memory for communicating with several peripheral devices, a direct memory access (DMA) circuit may be used to interface between each of the peripheral devices and the memory. The DMA circuit provides a general purpose method for communicating data between peripheral devices and the memory in a data processing system. By using the DMA circuit, the central processing unit is not required in accessing the memory for the required information. However, the central processing unit must temporarily halt operation while a memory transfer is taking place.
A dedicated queue memory uses less circuitry and typically does not require intervention by a central processing unit (CPU) to perform a memory access as compared to a DMA circuit. However, the queued memory is not as general as the DMA circuit and is typically designed for a specific peripheral device. Because of the different data interface requirements of each of the peripheral devices which may be implemented in a data processing system, the queued memory used for each of the peripheral devices must be designed for use only in a respective peripheral device. Therefore, the queued memory is included as a part of each peripheral device and must be redesigned each time the peripheral device is modified. Such specificity often results in increasing overhead during a design phase of manufacture.
In each of the DMA and the queued memory, an internal system bus is required to transfer data. In both types of systems, two options for using the internal system bus typically exist. In a first option, the central processing unit of the system in which either is implemented must be interrupted when a data transfer operation must be executed. The first option immediately halts a current operation when the data transfer must be executed. In a second option, the DMA and the queue memory wait an indefinite amount of time until a "free" cycle is available on the internal system bus. The "free" cycle occurs when the central processing unit is not using the internal system bus. However, while the second option does not interrupt important operations of the central processing unit, the DMA and the queued memory are required to wait an indefinite period of time before transferring data. In some situations, the period of time may be such that the data to be transferred is no longer valid and must be accessed again from the appropriate memory device.
Therefore, a need exists for a memory system which efficiently and effectively transfers data as required by both the central processing unit and a memory device which is implemented therein. Currently, solutions to this problem do not allow for efficient resolution of the problem, but require that either the central processing unit or the memory device (DMA or queued memory) operate in a less than efficient manner.